Low power and high performance dynamic CMOS XOR/XNOR gate design
نویسندگان
چکیده
Article history: Available online 17 February 2011 Keyword: Dynamic XOR/XNOR Gate Leakage Power Variation 0167-9317/$ see front matter 2011 Elsevier B.V. A doi:10.1016/j.mee.2011.02.068 ⇑ Corresponding author. Tel.: +86 15001166864. E-mail address: [email protected] (J. A hybrid network technique is proposed in dynamic CMOS XOR/XNOR gate to reduce the power consumption, save the layout area and avoid signal skew. Compared to the standard N type dynamic gate with similar delay time, the leakage power, dynamic power and layout area of the novel XOR/XNOR gate are reduced by up to 51%, 13% and 24%, respectively. Also, the inputs and clock signals combination static state dependent leakage characteristics of three dynamic CMOS XOR/XNOR gates are analyzed thoroughly. Finally, their robustness to noise, process and temperature variations are discussed. 2011 Elsevier B.V. All rights reserved.
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